In recent years, as the feature size of semiconductor integrated circuit devices (which will be hereinafter referred to as “semiconductor devices”) becomes smaller, a combination of a copper interconnect and an insulation film having a low dielectric constant, i.e., a so-called low-k film has been adopted as a multi-layer interconnect of a semiconductor device. With use of such a multi-layer interconnect, RC delay and power consumption can be reduced. Furthermore, to increase the degree of integration, function and operation speed of a semiconductor device, use of a low-k film having an even lower dielectric constant than that of those presently used is examined.
A copper interconnect is usually formed using a damascene technique. Damascene techniques include a single damascene technique in which an interconnect and a via plug are alternately formed and a dual damascene technique in which an interconnect and a via plug are simultaneously formed.
Hereinafter, a method for forming a multi-layer interconnect by a damascene technique will be described with reference to FIGS. 11(a) and 11(b).
As shown in FIG. 11(a), a first insulation film 102 is formed on a silicon substrate 101 and then a first copper interconnect 104 which is a copper interconnect of a lower layer including a first barrier metal film 103 is formed in the first insulation film 102. On the silicon substrate 101, a transistor and the like (not shown) are formed. Subsequently, a dielectric barrier film 105 for preventing diffusion of copper and a second insulation film 106 are formed in this order over the first insulation film 102 and the first copper interconnect 104. Thus, an insulation layer including the diffusion film 105 and the second insulation film 106 is obtained.
Next, a via hole 106a is formed in the dielectric barrier film 105 and the second insulation film 106 and an interconnect trench 106b is formed in the second insulation film 106. Thus, a recess portion 106c including the via hole 106a and the interconnect trench 106b is obtained. The via hole 106a and the interconnect trench 106b are formed by process steps of forming a dual damascene interconnect trench (i.e., the recess portion 106c including the via hold 106a and the interconnect trench 106b) using known lithography, etching, ashing and cleaning. In general, a method in which after formation of the via hole 106a, the interconnect trench (trench) 106 is formed has widely used (see, for example, Patent Reference 1).
Next, a second barrier metal 107 is formed so as to cover surfaces of the recess portion 106c using physical vapor deposition (PVD) or like film formation method.
Next, on the second barrier metal film 107, a copper seed layer is formed by physical vapor deposition and then a copper film is formed by copper electroplating using the copper seed layer as a seed so as to fill the recess portion 106c and cover an entire surface of the second insulation film 106. Subsequently, parts of the copper film and the second barrier metal film 107 located on the second insulation film, except for parts thereof located inside the recess portion 106c, are removed by chemical mechanical polishing (CMP) to form a second interconnect 108 including a via plug. Note that the second copper interconnect 108 may be an interconnect, a via plug, or a combination of an interconnect and a via plug. A multi-layer interconnect can be formed by repetition of a series of the process steps described above.
Materials used for the second insulation film 106 and the second barrier metal film 107 will be described with reference to FIG. 11(b).
As the dielectric barrier film 105, a silicon nitride film, a silicon nitride carbide film, a silicon carbide oxide film or the like is used. The copper dielectric barrier film 105 has the function of preventing diffusion of copper forming the first interconnect 104 which is a lower layer into the second insulation film 106.
As the second insulation film 106, a silicon oxide film, a fluorine-doped silicon oxide film, a silicon oxide carbide film, or an insulation film formed of an organic film is used. That is, the second insulation film 106 may be a film selected from the group consisting of the films shown in FIG. 11(b) (note that in FIG. 11(b), the case where the second barrier metal film 107 is a metal nitride film is shown). Each of the films may be a film formed by chemical vapor deposition or a SOD (spin on dielectric) film formed by spin coating.
In general, copper is easily diffused in an insulation film such as silicon oxide film by heat or an electric field. This tends to be a cause of deterioration of transistor characteristics. Moreover, copper has poor adhesion with an insulation film. Therefore, in forming a copper interconnect, a method in which a barrier metal film of a tantalum film or a tantalum nitride film is formed between copper and an insulation film to prevent diffusion of copper into the insulation film and also to improve adhesion between the insulation film and copper has been proposed (see, for example, Patent Reference 2). A tantalum film or a tantalum nitride film is used as a single layer or a lamination layer structure.
However, for example, in the above-described example, when a refractory metal such as tantalum is used as the second barrier metal film 107, adhesion between the second insulation film 106 in which the recess portion 106c is formed and the refractory metal film is poor. To cope with the problem of such poor adhesion, for example, if a tantalum film is used as the second barrier metal film 107, a tantalum nitride film is formed between the second barrier metal film 107 made of a tantalum film and the second insulation film 106 to improve poor adhesion. But, in this manner, sufficient adhesion is still not obtained.
Moreover, when a tantalum film is used as the second barrier metal film 107, the tantalum film is oxidized in forming copper by electroplating, so that a high resistance tantalum oxide film is formed. For this reason, increase in interconnect resistance can not be avoided.
Moreover, when a tantalum nitride film is used as the second barrier metal film 107, the tantalum nitride film is not oxidized. However, a tantalum film has a high resistance and adhesion with copper is poor.
Furthermore, when a titanium film or a titanium nitride film is used as the second barrier metal film 107, the same problems arise as when a tantalum film or a tantalum nitride film is used.
In view of the above-described problems, a metal such as ruthenium and iridium which itself or whose oxide has a low resistance is used as the second barrier metal film 107 to achieve reduction in resistance of the second barrier metal film 107 (see, for example, Patent Reference 3 and Patent Reference 4), and this technique has attracted interest. In general, such metals are formed by atomic layer deposition or chemical vapor deposition.
(Patent Reference 1) Japanese Laid-Open Publication No. 10-223755
(Patent Reference 2) Japanese Laid-Open Publication No. 2002-43419
(Patent Reference 3) Japanese Patent Publication No. 3409831
(Patent Reference 4) Japanese Laid-Open Publication No. 2002-75994